MIPS R2000 multi-cycle microcode spec

Starting at bit 31:
next[31:30]		# 00=next, 01=0, 10=d1, 11=d2
PCSource[29:28]	# 00=ALUres, 01=ALUOut, 10=jump target, 11=0

ALUOp[27:26]	# 00 for add, 01 for sub, 10 for func
ALUSrcB[25:24]	# 00=B, 01=#4, 10=immed, 11=immed*4

ALUSrcA[23]		# PC or A to A
RegDst[22]		# I[16:20] or I[11:15] to WA
MemToReg[21]	# ALUOut or mdr to WD
RegW[20]

IorD[19]		# PC or ALUOut to Addr
MemW[18]
MemR[17]
IRWrite[16]

Cond[15]		
PCWrite[14]		# PCWrite = PCWrite OR (Cond AND ALUzero)

extra[13:0]

microcode:
0: fetch:		IorD=0, MemR, IRWrite					# read [PC]
				ALUSrcA=0, ALUSrcB=01, ALUOp=00			# PC+=4
				PCSource=00, PCWrite							

1: decode:		ALUSrcA=0, ALUSrcB=11, ALUOp=00			# branch target
				(and regfetch)
				next=10									# dispatch1

2: mem1:		ALUSrcA=1, ALUSrcB=10, ALUOp=00			# mem addr
				IorD=1									# prep for store
				next=11									# dispatch2

3: lw1:			ALUSrcA=1, ALUSrcB=10, ALUOp=00			# maintain ALU
				IorD=1, MemR							# read [ALUOut]

4: lw2:			ALUSrcA=1, ALUSrcB=10, ALUOp=00			# maintain ALU
				IorD=1, MemR							# maintain mem
				RegDst=0, MemToReg=1, RegW				# write to dest reg
				next=01									# fetch

5: sw1:			ALUSrcA=1, ALUSrcB=10, ALUOp=00			# maintain ALU
				IorD=1, MemW							# write [ALUOut]
				next=01									# fetch

6: rform1:		ALUSrcA=1, ALUSrcB=00, ALUOp=10			# A op B

7: rform2:		ALUSrcA=1, ALUSrcB=00, ALUOp=10			# maintain ALU
				RegDst=1, MemToReg=0, RegW				# save to reg
				next=01									# fetch

8: iform1:		ALUSrcA=1, ALUSrcB=10, ALUOp=00			# A + Immed

9: iform2:		ALUSrcA=1, ALUSrcB=10, ALUOp=00			# maintain ALU
				MemToReg=0, RegW						# save to reg
				next=01									# fetch

10: beq1:		ALUSrcA=1, ALUSrcB=00, ALUOp=01			# compare
				PCSource=01, Cond						# write PC on equal
				next=01									# fetch

11: jmp1:		PCSource=10, PCWrite					# jump to addr
				next=01									# fetch


assembled microcode:
0/ 0000 0001 0000 0011 0100		01034000
1/ 1000 0011 0000 0000 0000		83000000
2/ 1100 0010 1000 1000 0000		c2880000
3/ 0000 0010 1000 1010 0000		028a0000
4/ 0100 0010 1011 1010 0000		42ba0000
5/ 0100 0010 1000 1100 0000		428c0000
6/ 0000 1000 1000 0000 0000		08800000
7/ 0100 1000 1101 0000 0000		48d00000
8/ 0000 0010 1000 0000 0000		02800000
9/ 0100 0010 1001 0000 0000		42900000
a/ 0101 0100 1000 0000 1000		54808000
b/ 0110 0000 0000 0000 0100		60004000

dispatch 1 from step 1, decode
targets:
mem1	0x2		ops 0x23 and 0x2b
rform1	0x6		op=0
beq1	0xa		op=4
jmp1	0xb		op=2
iform1	0x8		op!=0

dispatch 2 from step 2, mem1
targets:
lw1		0x3		op=0x23
sw1		0x5		op=0x2b