The single-cycle implementation understands add, sub, addi, slt, beq, nop, lw, and sw. Branching is a two-cycle operation, resulting in the pre-branch execution of the instruction following the branch instruction.
The multi-cycle implementation understands add, sub, addi, slt, beq, j, nop, lw, and sw. Branching now operates normally. This processor is capable of running faster than the single-cycle version, because the clock no longer has to be slow enough for everything to happen in one cycle.
This multi-cycle processor was designed for the DLX instruction set, as described in Hennessey and Patterson's Computer Architecture: A Quantitative Approach. This version implements everything except traps/exceptions, non-word memory access, and floating-point operations. It is capable of running reasonably complex assembly-language programs, such as the one provided for computing prime numbers. See the DLX instruction reference page for details.
The PostScript and PDF files are now showing MUXes labeled correctly, thanks to a bug fix in TKGate 1.6h.
Parts of Patterson and Hennessey's Computer Organization and Design: The Hardware/Software Interface were used extensively as the basis for these processor designs.
Jeremy Weatherford
xidus@xidus.net
http://xidus.net